1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit device and a method of manufacturing the same in which via plug corrosion can be prevented by allowing a sufficient distance between a fuse opening area and a via plug.
2. Description of the Related Art
Generally, semiconductor manufacturing processes include a fabrication process (hereinafter called FAB process), an electrical die sorting process (hereinafter called EDS process), an assembly process and a test process, and are explained as follows.
During the FAB process, fully functional electrical circuits on a semiconductor wafer are attained by repeated processes of diffusion, photolithography, etching and thin film formation. After etching of a passivation layer, the final step in FAB process, the EDS process is being performed. The EDS process determines whether each chip on the semiconductor wafer is good or bad by an electrical test that includes a pre-laser test step which detects a defective chip and generates corresponding data, a laser repairing step which repairs the defective chip by a laser beam according to the data, a post-laser test step which selectively checks the repaired chip and a back-grinding step which grinds backside of a fabricated wafer with a diamond wheel.
During the laser repairing process, a defective memory cell is repaired by cutting a fuse which is connected to the defective memory cell using a laser beam and substituting a redundant memory cell in a chip for the defective memory cell. The fuse is also used to activate a redundant memory cell for substituting a defective memory cell.
In a conventional memory redundancy technology, a fuse, consisting of polysilicon or a silicide, is formed as a part of an interconnection layer on a field oxide. At present, RC delay in a chip becomes a major factor determining the chip performance speed with increasing density of semiconductor devices and the resulting strict design rule. Accordingly, a multi-layer interconnection structure and a fuse technology, in which a part of the uppermost layer is used as a fuse, are utilized.
FIG. 1 is a plan view illustrating a fuse area in a conventional semiconductor device. FIG. 2 and FIG. 3 are cross sectional views taken along line A-Axe2x80x2 in FIG. 1 illustrating a conventional method of forming a fuse in a semiconductor integrated circuit device.
Referring to FIG. 2, after depositing aluminium (Al) on an insulation layer (not shown) formed on a semiconductor substrate (not shown) in which a certain configuration of circuits is formed, a lower interconnection metal layer (12) is formed by patterning the aluminium layer by a photo-etching method. Subsequently, a first barrier metal layer (14) composed of a titanium (Ti) layer and a titanium nitride (TiN) layer is formed. After forming an inter-metal dielectric layer (16), which is formed of an insulation material such as an oxide, on the first barrier metal layer (14), a via (18) exposing a portion of surface of the lower interconnection metal layer (12) is formed by patterning the inter-metal dielectric layer (16). Thereafter, a metal layer, such as a tungsten (W) layer, is deposited thick enough to fill up the via (18) by chemical vapor deposition (CVD). Then, such a tungsten (W) layer is polished by chemical mechanical polishing (CMP) until the inter-metal dielectric layer (16) is exposed so as to form a metal plug such as tungsten (W) plug (20) filling up the via (18).
A second barrier metal layer (22) is formed by depositing a titanium (Ti) layer to a thickness of about 150 xc3x85, and a titanium nitride (TiN) layer to a thickness of about 650 xc3x85, consecutively by sputtering or chemical vapor deposition (CVD) method on the inter-metal dielectric layer (16) and the tungsten plug (20). The second barrier metal layer (22) prevents an unwanted reaction between tungsten (W) and aluminium (Al). And a fuse is formed by exposing the surface of the second barrier metal layer (22) at a certain area.
After depositing an aluminium (Al) layer to a thickness of about 6000 xc3x85 on the second barrier metal layer (22), an upper interconnection metal layer (24) is formed by patterning the aluminium layer by photo-etching. An oxide deposited on the second barrier metal layer by a plasma enhanced chemical vapor deposition (PECVD) method functions as a first passivation layer (26). A second passivation layer (28) is formed by depositing silicon nitride (Si3N4) on the first passivation layer (26) by plasma enhanced chemical vapor deposition (PECVD).
Subsequently, the second passivation layer (28) and first passivation layer (26) are dry etched so as to define a fuse opening area (30) as illustrated in FIG. 1.
Referring to FIG. 3, the fuse area of the second barrier metal layer (22) is exposed by chemical etching, using a chemical etchant having a selectivity between the second barrier metal layer (22) and the upper interconnection metal layer (24) and the patterned second and first passivation layer (28,26) as an etching mask. At this time, the upper interconnection metal layer (24) under the first passivation layer (26) is also etched. Particularly, the thicker the interconnection metal layer (24) is, the more the interconnection metal layer under the first passivation layer is etched. Accordingly, if the distance (d1 in FIG. 1) between the fuse opening area (30) and the via (18) is short, tungsten plug (20) filling up the via (18) can be exposed.
As above, if photolithography step for forming a pad is performed with tungsten plug being exposed, charges are accumulated at the exposed tungsten plug during the ashing step using oxygen plasma. Consequently, the tungsten plug is corroded due to a strong electrochemical reaction at the surface of the tungsten plug when the tungsten plug is exposed to an organic stripper in a subsequent wet strip process. In worst case, all the tungsten plug (20) in the bottom portion of the via (18) can be in a chemical solution, which can lead to a contact failure.
It is, therefore, an object of the present invention to provide a semiconductor integrated circuit device in which a via plug is not exposed during the step of opening a fuse area such that the corrosion of the via plug can be prevented.
It is another object of the present invention to provide a semiconductor integrated circuit device manufacturing method by which a via plug is not exposed in the step of opening a fuse area so as to prevent the corrosion of the via plug.
The first object is accomplished by the semiconductor integrated circuit device characterized in comprising a first interconnection metal layer formed on a semiconductor substrate; an inter-metal dielectric layer formed on the first interconnection metal layer having a via exposing the first interconnection metal layer; a via plug filling up the via; a metal layer for a fuse and a second interconnection metal layer consecutively formed on the via plug and the inter-metal dielectric layer. According to the present invention, a fuse opening area that exposes the metal layer for a fuse is positioned more than twice the thickness of the second interconnection metal layer from the via.
Preferably, a first passivation layer which exposes the fuse is formed on the second interconnection metal layer.
Preferably, a second passivation layer is formed on the first passivation layer.
Preferably, the second passivation layer encloses the first passivation layer, the second interconnection metal layer, the metal layer for a fuse.
To accomplish the second object, the present invention in manufacturing method of a semiconductor integrated circuit device in which multiple interconnection metal layers are connected through a via comprises steps of consecutively forming a metal layer for a fuse and a interconnection metal layer on the via; forming a first passivation layer on the interconnection metal layer; patterning the first passivation layer to define a fuse opening area which is positioned more than twice the thickness of the interconnection metal layer from the via; and forming a fuse area by exposing the metal layer for a fuse by wet etching the interconnection metal layer using the first passivation layer as a mask.
Preferably, after forming the first passivation layer, a second passivation layer is formed on the first passivation layer and the second and first passivation layers are patterned to define a fuse area.
Preferably, after the step of forming a fuse area by exposing a metal layer, a second passivation layer is formed on the resulting structure.
Preferably, the first passivation layer is composed of an oxide and the second passivation layer is composed of a nitride.
Preferably, the thickness of the first passivation layer is greater than 3000 xc3x85. Preferably, the thickness of the second passivation layer is less than 8000 xc3x85.